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PILZ CPU PSS SB CPU 3技術參數
最近更新時間：2018-7-10
提 供 商：上海茂碩機械設備有限公司資料大小：229.2KB
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PILZ CPU PSS SB CPU 3技術參數 Central Processing Unit with SafetyBUS p® Connection
PSS SB CPU 3, PSS1 SB CPU 3
Technical details PSS SB CPU 3 PSS1 SB CPU 3
Function Central processing unit for
decentralised applications
Application range Failsafe applications conforming to
EN 954-1, 11/94, DIN V 19 250, 01/89,
DIN VDE 0116, EN IEC 61508
Electrical data
Processing time Typ. 0,5 ms for 1000 instructions
Real-time clock Integrated into ST section
Alarm processing Max. 32 alarms in FS section
Flags 2048 (ST section), 5184 (FS section)
Timers 64 (ST section), 64 (FS section)
Time base 50, 100 ms, 1, 10 s, 1 min
Counters 64 (ST section), 64 (FS section)
Date memory Standard section: 170 kByte
Failsafe section: 64 kByte
(non-retentive)
Program memory Standard section:
Integral 512 kByte Flash-EPROM
Failsafe section: 512 kByte Flash-
EPROM
Display 4-digit
PILZ CPU PSS SB CPU 3技術參數
Serial interfaces, galvanically isolated RS 232/RS 485 for user and for
programming device
Termination for user adjustable
SafetyBUS p®
Transmission rate Max. 500 kBit/s
Cable runs Max. 3500 m
Transmission type Differential two-wire cable
Connection 9-pin D-Sub-coupling
Mechanical data
Size (H x W x D) 257 x 41 x 220 mm 265 x 41 x 218 mm
Weight 1260 g 620 g
Environmental data
Protection type (EN 60529, 02/00) IP 20
Ambient temperature 0...+60 °C
(EN 60068-2-14, 11/99)
Storage temperature -25...+70 °C
(EN 60068-2-1/-2, 03/95)
Climatic suitability max. 95 % r.h.
(DIN IEC 60068-2-3, 12/86)
Condensation Not permitted
Vibration to EN 60068-2-6, 04/95 Frequency range: 10...150 Hz
Amplitude: 0.075 mm, max. 1 g
Shock
EN 60068-2-27, 03/99 30g, 11ms
EN 60068-2-29, 04/93 10g, 16 ms
EMC EN 61000-6-2, 04/99
EN 55011, 08/00
Central processing unit with integral
test algorithms and redundant
design, for use as part of a modular
safety-related system with
connection to SafetyBUS p®.
Features
● SafetyBUS p® connection
● Failsafe modules have typeapproval
● Powerful CPU means programs
are processed at high speed
● Failsafe (FS) and standard (ST)
programs are processed
without feedback
● Approved blocks are available
for all key functions such as
emergency stopping, thereby
reducing development and
commissioning costs
● Programmable communications
interface available
Approvals
PSS SB CPU PSS1 SB CPU
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PILZ CPU PSS SB CPU 3技術參數